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Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language () and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - ), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - ) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of , IEEE 1364-2005.

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Creating transition coverage bins using a queue or dynamically

I want to write a transition coverage on an enumeration. One of the parts of that transition is a queue of the enum. I construct this queue in my constructor. Considering the example below, how would one go about it. In my coverage bin I can create…
Sparsh Gupta
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System Verilog Nested Associative Array

How do you declare an initialize a nested associative array in System Verilog? /* Creating an associative array(AA) called timings such that each key contains an AA with a list of relevant key value pairs */ typedef string timingObj…
Julito Sanchis
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How to optimize finding values in 2D array in verilog

I need to set up a function that determines if a match exists in a 2D array (index). My current implementation works, but is creating a large chain of LUTs due to if statements checking each element of the array. function result_type index_search (…
T100
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How to iterate all argument passed to a task or function in SV?

It is possible to iterate through all the argument that I passed to a system verilog task or function such as argv in c and @ARGV in Perl? Since I don't have any idea of how many argument that are going be passed into. test("name2", 1,2,3); //…
fieq.fikri
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How to fix 'port multiply driven' warnings System Verilog

I have an AXI UVC which can be configured to be either Master or Slave and an interface with 3 clocking blocks (mst_cb, slv_cb, mon_cb). I get warning messages telling me that a port is multiply driven. How do you fix these warning messages? I'm not…
je_pat
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Using SystemVerilog structs that contain parameters as input/output ports to a module

My struct contains parameters that vary per module. I'd like to use this struct to pass input/outputs to these modules. I'm using this for design so it has to be synthesizable and my toolchain doesn't support Interfaces unfortunately. For…
jkang
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How to do a logical operation per instance in a vector of instances

Say I have a module with inputs of N bits and a single bit that I instantiate like so: module foo ( input wire [N-1:0] x, input wire y ); foo u__foo ( .x(x), .y(x == something) ); And I want to instantiate M of them as a vector, and…
Charles Clayton
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Add delay between sampling and checking

I have written an assertion property. I want to add delay between sampling and checking action. Basically below assertion says that assert_sig should be stable when sig1 or sig2 1. property check_assert(assert_sig, assert_sig_dis); …
Jigar Vaidya
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Method to delete particular index in dynamic array

Is there any other method to delete a particular index value from the dynamic array? Here is my eg to delete index 2 of array a which I am storing it into array b module top; bit[3:0] a []; bit[3:0] b []; int k=0; initial begin …
Emman
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Usage of a super.body() variable is illegal as it's considered "not declared"

I extended the usage of my virtual task body() in a sequence class, and in the parent class declaration of body(), I declared a variable. However, upon using it in the extended class' body() , I faced a compilation error Identifier 'q' has not been…
El_Gahaf
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Streaming operators usage in the context of serializers in PHY

I have 8:1 serializers and de-serializers based on the data width in our RTL code.As of now we are using for loops for the data path loading and data path reading from the serializers. Can we use streaming operators for this functionality. Iam new…
Rama Krishna Meda
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how to control rounding mode of real number in systemverilog

I would like to write a test for FPU module and can't find out a way to change a rounding mode of real numbers in SystemVerilog. Does the system function or any easy method exist to do that? Thank you in advanced
Alexandr Bolotnikov
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Using an array find within an array find

Is there a way to use an array locator function as the condition to an array locator function? Something like the following: I know I can simply loop through the arrays but I'm hoping for a more concise method module tb; typedef struct { …
Arun D'souza
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Why not "mailbox" instead of "interface" in systemverilog testbench

I am new to systemverilog. I learned the functionality of "interface" to connect testbench and DUT but what I am thinking is why do I need to connect these two? Can't I simple pass the testcases generated by testbench to my DUT via "mailbox"? If…
Payal
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How do I change these modules so that the communication is bidirectional (inout)?

I'm simply not sure how to modify the code. I know i need to add an inout port but I don't know how to do it. I have watched multiple tutorials but I can't figure it out. module mem( input logic clk, we , // write enable bit, active…
mattycodes1995
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