Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
(summary adapted from Wikipedia)
Logic synthesis
Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.
When asking a question, please specify whether you are looking for a synthesizable solution.
Sometimes referred to as Verilog HDL, not to be confused with VHDL.
Standardization
Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.
Tags specific to Verilog
system-verilog system-verilog-assertions system-verilog-dpi uvm vpi icarus iverilog verilator
