Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

2591 questions

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packed vs unpacked vectors in system verilog

Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this: node [range_hi:range_lo]x; and others that are defined like this: node y[range_hi:range_lo]; I understand that x is defined as packed, while y is…

vector system-verilog

asked Jan 25 '09 at 12:35

Nathan Fellman

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Difference among always_ff, always_comb, always_latch and always

I am totally confused among these 4 terms: always_ff, always_comb, always_latch and always. How and for what purpose can these be used?

system-verilog

asked Apr 16 '14 at 06:30

user2138826

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6 answers

How to interpret blocking vs non blocking assignments in Verilog?

I am a little confused about how blocking and non blocking assignments are interpreted when it comes to drawing a hardware diagram. Do we have to infer that a non blocking assignment gives us a register? Then according to this statement c <= a+b , c…

verilog system-verilog

asked Jan 11 '11 at 01:19

infinitloop

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2 answers

Indexing vectors and arrays with +:

I am seeing a code in SystemVerilog which has something like this: if(address[2*pointer+:2]) do_something; How should I understand the +: when indexing this vector? I found that it is called bit slicing, but I can't find an explanation about it.

system-verilog

asked Aug 05 '13 at 20:56

DOS

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8 answers

VHDL/Verilog related programming forums?

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC?

vhdl verilog system-verilog systemc

asked Jun 30 '10 at 19:03

prosseek

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2 answers

ADDRESS WIDTH from RAM DEPTH

I am implementing a configurable DPRAM where RAM DEPTH is the parameter. How to determine ADDRESS WIDTH from RAM DEPTH? I know the relation RAM DEPTH = 2 ^ (ADDRESS WIDTH) i.e ADDRESS WIDTH = log (base 2) RAM DEPTH. How to implement the log (base 2)…

verilog system-verilog

asked Mar 11 '11 at 06:20

Ashwini

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2 answers

What is `+:` and `-:`?

What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example: logic [15:0] down_vect; logic [0:15] up_vect; down_vect[lsb_base_expr +: width_expr] up_vect [msb_base_expr +: width_expr] down_vect[msb_base_expr…

verilog system-verilog

asked Jul 22 '13 at 00:36

e19293001

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5 answers

Difference of SystemVerilog data types (reg, logic, bit)

There are different data types in systemverilog that can be used like the following: reg [31:0] data; logic [31:0] data; bit [31:0] data; How does the three of them differ?

system-verilog

asked Nov 08 '12 at 03:42

e19293001

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Verilog: How to instantiate a module

If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top? top: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0]…

verilog system-verilog

asked Nov 19 '13 at 08:44

Morgan

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2 answers

$size, $bits, verilog

What is the difference between $size and $bits operator in verilog.? if I've variables, [9:0]a,[6:0]b,[31:0]c. c <= [($size(a)+$size(b)-1]-:$bits(b)]; What will be the output at 'c' from the above expression?

arrays verilog system-verilog

asked Nov 12 '12 at 08:19

Suhas

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2 answers

How to define and initialize a vector containing only ones in Verilog?

If I want to declare a 128 bit vector of all ones, which one of these methods is always correct? wire [127:0] mywire; assign mywire = 128'b1; assign mywire = {128{1'b1}}; assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

verilog system-verilog register-transfer-level

asked Sep 30 '13 at 23:12

Veridian

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How to create a string from a pre-processor macro

I have a preprocessor macro that represents a hierarchical path into my design. Example: `define HPATH top.chip.block I need to construct a string which holds the value of `HPATH, so in my example the string should equal top.chip.block. Is there a…

macros verilog system-verilog

asked Mar 12 '13 at 22:03

dwikle

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2 answers

What SystemVerilog features should be avoided in synthesis?

SystemVerilog introduced some very useful constructs to improve coding style. However, as one of my coworkers always says, "You are not writing software, you are describing hardware." With that in mind, what features of the language should be…

verilog system-verilog

asked Dec 01 '13 at 13:48

nguthrie

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2 answers

What's the best way to tell if a bus contains a single x in verilog?

I have a test bench that monitors a bus. Some of signals within the bus can be 1'bx. For a variety of reasons I need to know if any of the signals within the bus are 1'bx. What's the best way to test (not for synthesis -- only for simulation…

verilog system-verilog

asked Jul 01 '13 at 20:23

Doov

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2 answers

Incrementing Multiple Genvars in Verilog Generate Statement

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in a single generate loop. I'm trying the following: genvar i,j; //Level 1 generate j=0; for (i=0;i<128;i=i+1) begin: level1Comp …

hardware syntax-error verilog system-verilog hdl

asked Mar 05 '12 at 04:46

Adam

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