Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

2591 questions

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1 answer

assign statement using virtual interface variable

I want to connect the module variable to the port in virtual interface using assign statement. I created one interface and set it as virtual in config_db in my top module. I got the virtual interface via config_db in another module and trying to…

system-verilog uvm

asked Mar 23 '19 at 11:55

Somesh

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1 answer

Is there a function to concatenate a queue of strings in SystemVerilog?

Generally, one could do this: string a; a = {a, " first"}; a = {a, " second"}; a = {a, " third"}; From what I understand, this means that a is continuously reallocated for the concatenated string each time. Is there a magical join function that'll…

system-verilog

asked Mar 20 '19 at 19:02

Arun D'souza

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1 answer

Problem with creating structural modules using interfaces (SystemVerilog)

I'm new in SystemVerilog, and currently learn interfaces, and I ran into problem with structural modules. So, for example, i have created interface interface BusInterface #(parameter N = 3) (input logic i_clk); logic i_RESET; logic …

verilog fpga system-verilog

asked Mar 16 '19 at 16:17

Ruslan

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1 answer

How to reseed the RNG of a static process?

I have an always process running in my testbench that calls $urandom_range() Is it possible to reseed this while im running my testbench? I guess it has something to do with srandom but can't get it to work.

verilog system-verilog

asked Mar 15 '19 at 08:52

Moberg

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Parametrized uvm sequence item to adjust size

I have an issue and I am out of ideas on how to resolve it. I have a class that contains an array called data. This dynamic array can be of parametrized packed width - either 8, 16, or 32 bits for example. class MyItem#(int WIDTH=8) extends…

system-verilog verification uvm

asked Mar 12 '19 at 22:30

noobuntu

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1 answer

SystemVerilog always_comb does not re-evaluate if the implied sensitivity list changes

Here's a piece of code with 3 different always statement which should be synthesizable. The issues is with the following: always_comb begin c_cntr1 = cntr1; c_func_val1 = diff (0, c_cntr1); if (read) c_cntr1 = cntr1+1; …

system-verilog evaluation synthesis register-transfer-level

asked Mar 12 '19 at 19:22

user9906612

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2 answers

Trying to set all one's in register fields with similiar name in a register

I am trying to set a uvm register fields in SystemVerilog. Here are my register fields: TXA TXA1 RSVD T4AMP I am interested in setting all ones into the register fields starting with TXA. I have used the below code to use regex uvm_reg_field…

system-verilog uvm

asked Mar 11 '19 at 20:58

sai kiran

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1 answer

how to access sequential register based offset using uvm?

i need to access 4 same register that are only different on offset. reg layout: reg0: 0x10 reg1: 0x14 reg2: 0x18 reg3: 0x20 and i use an autotool to generate uvm_block like following class dut_reg_block extend uvm_reg_block REG0 reg0; REG1…

system-verilog uvm

asked Mar 11 '19 at 06:49

Jingbo Zhang

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2 answers

Combining coverpoints to create an aggregate

`define A 'd1 `define B 'd2 `define C 'd3 `define D 'd4 `define E 'd5 `define F 'd6 `define I 'd7 `define J 'd8 module testModule(input clk, input CReset, input[4;0] Opcode_P0I1, …

code-coverage system-verilog uvm cadence

asked Mar 08 '19 at 18:46

Sparsh Gupta

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1 answer

How to return an array from a function with the same name as that of the function in system verilog?

module rev_array; int array_in[10]={0,1,2,3,4,5,6,7,8,9}; typedef integer array[9:0]; function array reverse(int array_in[10]); for(int j=$size(array_in)-1,int i=0;j>=0;j--,i++) begin reverse[j]=array_in[i]; …

system-verilog

asked Mar 07 '19 at 21:17

Grace90

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1 answer

I want to reverse and return an array in a function in system verilog, i tried below code and i am getting following error

module rev_array; initial begin int array_in[10]={0,1,2,3,4,5,6,7,8,9}; typedef integer array[9:0]; function array reverse(int array_in[10]); array reverse; for(integer i=0;i<$size(array_in)-1;i++) begin for(int…

system-verilog

asked Mar 06 '19 at 22:44

Grace90

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1 answer

Systemverilog cross coverpoint syntax question

Hi I am new to stackoverflow and systemverilog/uvm. I am currently trying to get the a cross coverpoint to catch the condition that (a==b) && (c==d), regardless of what value they are. I have tried the following crosses and none of them seem to be…

system-verilog uvm

asked Mar 05 '19 at 13:02

DK_513

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1 answer

Why is my System Verilog Dynamic Array sum constraint is not working? (Run on EDA Playground (Aldec Tool Riviera Pro 2017)

Why is my System Verilog Dynamic Array sum constraint is not working? (Run on EDA Playground (Aldec Tool Riviera Pro 2017) ///////////////////////////////////// /////======================== class c ; string name; rand logic [4:0] len; rand…

system-verilog

asked Mar 03 '19 at 03:05

romi

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1 answer

How to end all outstanding objections in OVM

I am in run phase and lets say I have raised 20 objections. I want to end all these 20 objections already raised and raise 20 new objections in the same phase without jumping to the next phase. Can someone please suggest how to achieve this?

system-verilog uvm

asked Mar 01 '19 at 05:11

user1978273

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3 answers

Is it possible to have two instance have same name in the netlist?

Is it possible to have two flops/any other instances have the same name in the netlist? Considering that there is no hierarchy, say I have a design of 10M instances and there exists an flop called foo, is it possible that another flop have same name…

verilog system-verilog vlsi netlist

asked Feb 27 '19 at 06:16

Hemant Bhargava

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