29

I am totally confused among these 4 terms: always_ff, always_comb, always_latch and always. How and for what purpose can these be used?

Morgan
  • 18,407
  • 6
  • 54
  • 78
user2138826
  • 301
  • 1
  • 3
  • 4

1 Answers1

37

always is the main type of process from Verilog, the other is an initial which is ran once at the start of a simulation.

always_ff @(posedge clk) :
Represents a flip-flop (ff), the process is triggered (executed) on every positive edge of the clock. This replaces always @(posedge clk). This is the only type where non-blocking (<=) assignments should be used, as this mimics the way a flip-flop transfers data.

always_ff @(posedge clk) begin
  a <= b;
end

always_latch : is for representing latches.

Usage would be :

always_latch begin
  if (enable) begin
     a_latch = something;
  end
  //No else clause so a_latch's value
  //is not always defined, so it holds its value
end

This replaces :

always @* begin
  if (enable) begin
     a_latch = something;
  end
  //No else clause so a_latch's value
  //is not always defined, so it holds its value
end

always_comb:
Is for combinatorial logic, it is replacement for always @* when you do not want a latch. Now we can now differentiate our design intent between when we want and do not want latches.

The SystemVerilog names always_ff, always_latch and always_comb have stricter criteria for when they are triggered, this means the chance for RTL to Gate level (post synthesis) mismatch is reduced. It does mean the are not 100% equivalent to there always @ counter part and may change some simulation behaviour.

skrrgwasme
  • 8,245
  • 11
  • 47
  • 71
Morgan
  • 18,407
  • 6
  • 54
  • 78
  • 11
    `always_comb` is not equivalent to `always @*`, and you should no longer be using `always @*`. The biggest reason is that `always @*` does not work when constants or parameters are involved in the logic. They do not generate events to trigger the execution of the block. `always_comb` guarantees execution at time 0. – dave_59 Apr 16 '14 at 14:57
  • Thanks @dave_59 I tried to cover the exact equality with my last paragraph. They are SystemVerilog and IPs are often design to be backwards compatible with Verilog, so usage of `always @*` will continue. Considering how many beginners post questions with manual sensitivity list I think we have a way to go before `always_comb` becomes the norm. – Morgan Apr 16 '14 at 17:28
  • 1
    Yep, just think how long it is taking people to switch from using comment pragmas like `//synthesis translate on` to using ` `ifdef SYNTHESIS`. It's been over 25 years since `ifdef was added to Verilog. – dave_59 Apr 17 '14 at 05:23
  • 1
    @Morgan: The IEEE standard uses `always_latch` with non-blocking assignments. Any specific reason you are using blocking assignments in your reply? – Ari Oct 23 '14 at 18:51
  • @Ari I see `always_latch` as an extension of `always @*`. `<=` Models flip-flop behaviour and when a latch is open it is transparent so I think `=` is more appropriate. and I had not noticed that they use non-blocking (`<=`) in the LRM. – Morgan Oct 23 '14 at 19:20