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Questions tagged [alu]

ALU stands for Arithmetic logic unit (ALU) that performs arithmetic and logical operations for computer systems.

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Proteus error:logic race conditions detected during transient analysis

I’m trying to design a simple alu that get two 5-bit number and return the result of adding them or subtract or multiply or divide. With using ICs ,it goes well.However I want to design everything myself. In designing divide I get error : logic race…
Melika Z
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Logisim ALU Red Lines - Not Understanding Causes and How to Fix

I'm working on a project where I need to create my own CPU for a specific instruction subset of MIPS. I will admit I thought I understood the single-cycle datapath until this project. So excuse my confusion. My issue is with my ALU. The ALU…
Pwrcdr87
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Making a 16-bit ALU using 1-bit ALUs

Hello I am trying to create a 16-bit ALU from several 1-bit ALUs I created a package named basic_alu1 which contains a component of the 1-bit ALU.The code for this is: library ieee; use ieee.std_logic_1164.all; package basic_alu1 is component alu1 …
user6345302
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ALU with Structural VHDL??

I am trying to create an ALU using structural code in VHDL. The code was originally in Verilog and then I manually changed it all over to VHDL, so that's why I have many separate files...but in theory these should work. The following are the…
David C
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'sra' not working in VHDL

I am making a component which takes in input of 32 bits and a control input of 7 bits. What this component does is that it looks at last 2 bits of S and for S = 00, it does logical shift left on inp S = 01, it does logical shift right on inp S =…
Ankit Shubham
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Input Output for 8-bit ALU using FPGA board

I am a newbie to xilinx so please excuse any stupidities in the code. Ah so I am trying to design an 8-bit ALU and the module is working perfectly on the simulation but we need to take inputs and display outputs on FPGA board. Technically I should…
Maira Muneer
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Simple sum in IJVM

Suppose we need to make a sum of two binary numbers in ijvm, for example: 100 + 11 = 111 Translating all in ijvm: ILOAD arg1 //100 ILOAD arg2 // 11 IADD ISTORE i Without making any changes to the code, what the content of the…
user4252099
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How do I wire modules?

I have written all the code, including the modules, but I can't figure out how to wire the modules to the main program. The ALU should be: A (4bits) and B (4bits) as inputs, sel (3bits) 1st Module When sel = 000 => Add/ sel= 001 => Sub (A+B or…
L.L
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McPAT: ALU per access power computation

I am working on McPAT. I wanted to know the formula they used in their power calculation of ALU and FPU. In the logic.cc file, while initializing the ALU and FPU, they update a variable called per_access_energy. This variable is later used to…
Luniam
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Is my VHDL 1-bit Behavioral ALU complete?

This is my first time writing VHDL code, and I'm wondering if this simple ALU VHDL code is complete. Everything I can find is for more complex ALUs, but I just need to write this simple one. The problem is as follows: Write a behavioral model that…
Drac
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When to break down VHDL?

Although I'm somewhat proficient in writing VHDL there's a relatively basic question I need answering: When to break down VHDL? A basic example: Say I was designing an 8bit ALU in VHDL, I have several options for its VHDL implementation. Simply…
Emphacy
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32 Bit ALU in VHDL Carry Out

I'm supposed to write a simple 32 Bit Alu in VHDL. Everything is working fine, except for two things. The ALU is supposed to have an carry out and overflow flag and I cant't figure out how to implement that. First a general question. The circuit…
PeterPanter
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VHDL : signal initialisation

I'm a beginner at VHDL and I have problems when to decide whether I should initialize my signal or not... Here's an exemple : entity tatoo is port ( clk, reset : in std_logic; opcode : in…
ZouZou
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How to design a simple Adder with separate carry and borrow flags?

I am implementing a simple adder. However, I have a need for a bit of a unique twist. What I'm implementing is a "roll over" feature across a Code Segment(CS) register and an Instruction Pointer(IP) register. So, when you do a relative jump by +20,…
Earlz
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n-bit ALU in scheme

I'm making n-bit ALU in scheme and I have a 1-bit ALU so far. Can someone tell me how to approach this problem? Here are the instructions for it: The format of the procedure is (ALUn selection x1 x2 n) where the first parameter,…
Regina
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