Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1289 questions

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7 answers

Programming VHDL on Linux?

Anyone knows good environment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux?

linux vhdl xilinx intel-fpga

asked Jun 11 '10 at 17:53

Daniel M.

votes

2 answers

Why does this code for incrementing an uint8_t include `& 0xFF`?

When reading through some example codes for DMAs from Xilinx, I came across this piece of code: value = (value + 1) & 0xFF where value is an uint8_t. What is the point of the & 0xFF? Why not simply write value = value + 1?

c embedded xilinx

asked Feb 04 '15 at 13:42

TheFisherman

1,129
2
10
15

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3 answers

Flush cache to DRAM

I'm using a Xilinx Zynq platform with a region of memory shared between the programmable HW and the ARM processor. I've reserved this memory using memmap on the kernel command line and then exposed it to userspace via mmap/io_remap_pfn_range calls…

linux-kernel arm xilinx zynq

asked Sep 19 '13 at 14:01

Brian Magnuson

1,385
1
7
13

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3 answers

Easiest way to use DMA in Linux

I'm a EE and for a project at uni I'm developing hardware assisted image/video filtering on an FPGA (Xilinx ZYNQ), said device also has a dual core ARM A9 processor inside and more importantly there is also an ARM Primecell PL330 DMA controller I'm…

c linux-kernel linux-device-driver embedded-linux xilinx

asked Dec 09 '15 at 20:29

Filippo Savi

votes

2 answers

Printing signed integer value stored in a variable of type reg

How do I print a signed integer value stored in an 8-bit register declared as: reg [7:0] acc; Using: $display("acc : %d", acc) It prints the unsigned value. What's the correct syntax for the $display function?

verilog xilinx

asked Feb 17 '12 at 07:56

Nullpoet

9,549
16
44
61

votes

1 answer

How to generate schematic file from verilog source in Xilinx

What I'm doing I started playing around with Xilinx ISE Design Suite and wrote simple Arithmetical Logic Units in verilog. Using verilog Unit Under Tests to create input and output signals for ISim, I verified, that the code works just as I want…

verilog xilinx

asked Apr 20 '11 at 17:38

Margus

18,332
12
51
101

votes

4 answers

How to initialize contents of inferred Block RAM (BRAM) in Verilog

I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as below: module ram( input clock, // System clock input we, // When high RAM sets data in input lines to given address …

verilog fpga xilinx vivado

asked Apr 13 '16 at 22:15

Paulo

votes

5 answers

How commonly used are the xilinx chips?

I'm beginning to learn embedded with C (and maybe some C++) and someone from the office said they're willing to donate a free xilinx chip they've got sitting on their shelf. I was thinking more along the lines of an Arduino, especially that the…

c++ c embedded arduino xilinx

asked Jul 26 '10 at 19:16

cooper

1,494
14
25

votes

1 answer

How to launch Xilinx ISE Web Pack under Ubuntu?

I've downloaded and successfully installed Xilinx ISE Web Pack 14.4 on Ubuntu 12.10 although I'm unable to launch it.

fpga xilinx

asked Feb 27 '13 at 18:40

Can

3,914
6
25
41

votes

1 answer

Vivado Synthesis hangs in Docker container spawned by Jenkins

I'm attempting to move our large FPGA build into a Jenkins CI environment, but the build hangs at the end of synthesis when run in a Docker container spawned by Jenkins. I've attempted to replicate the environment that Jenkins is creating, but when…

docker jenkins xilinx vivado

asked Apr 17 '19 at 17:27

harkness

votes

2 answers

Read a specific memory address via /dev/mem from the command line

For context, programming a driver to interact with an FPGA IP core on an embedded Linux (Yocto: krogoth) on a Xilinx board. For debugging purposes I would like to read out specific memory addresses from physical memory. /dev/mem looks promising. I…

embedded-linux yocto xilinx

asked Dec 08 '17 at 13:11

Moritz

1,645
1
15
25

votes

3 answers

How to add a Linux kernel driver module as a Buildroot package?

I am currently building an Embedded Linux for my Zybo Board from Xilinx. For this I use Buildroot. Now I want to add a driver, written in C, which can be used by a user program to write to some specific registers, enabling it to control some LEDs.…

c embedded-linux xilinx buildroot

asked Oct 28 '16 at 14:29

Daiz

votes

2 answers

Ideas for a flexible/generic decoder in VHDL

I want to create an address Decoder that is flexible enough for me to use when changing the number of bits of the selector and of the decoded output signals. So, instead of having a static (fixed input/output size) Decoder that looks something like…

vhdl fpga xilinx

asked Jan 24 '11 at 22:29

Erick Tejada

votes

3 answers

How to send data to AXI-Stream in Zynq from software tool?

I'm looking for a way to send some data from my software app written in C to AXI-Stream interface of Zynq. Something like open(/dev/axistream); send_data(data); I'm running Linux on the Arm part and now I want to connect it to the programmable…

linux arm fpga xilinx zynq

asked Jun 02 '15 at 13:25

Viktor Puš

votes

2 answers

Type conversion in VHDL: real to integer - Is the rounding mode specified?

While debugging the handling of user defined physical types in Vivado (read more), I found a different behavior for type conversions from real to integer. Here is my example code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use …

type-conversion vhdl xilinx xilinx-ise vivado

asked Jan 07 '15 at 16:17

Paebbels

13,346
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