Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

704 questions

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2 answers

ModelSim Message Viewer Empty

I'm currently using Modelsim 10.1 alongside ISE 13.4 and run a very simple test bench. All code is VHDL. I ran into trouble using VHDL's assert statement the other day: Errors and warnings are output to the transcript. However, there are no messages…

asked Mar 14 '12 at 19:55

FRob

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1 answer

VCD dump for vhdl simulation via modelsim. HOWTO?

It's the first time i try to generate a VCD and i am getting some troubles. I have a testbench called bench_minimips.vhdl that contain the entity sim_minimips. I want simulate it and get a VCD out of it. i am typing the following command in the…

simulation dump vhdl modelsim

asked Aug 05 '11 at 15:36

Stefano

3,733
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4 answers

Testing VHDL / FPGA Using Python and A Simulator

The standard way to test VHDL code logic is to write a test bench in VHDL and utilize a simulator like ModelSim; which, I have done numerous times. I have heard that instead of writing test benches in VHDL, engineers are now using Python to test…

python testing vhdl fpga modelsim

asked Mar 02 '16 at 01:24

DigitalOne

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1 answer

How to concatenate strings with integer in report statement?

I'm having trouble getting the following report statement to work: report "ERROR: instruction address '" & CONV_INTEGER(a(7 downto 2)) & "' out of memory range." severity failure; Where a is of type in std_logic_vector(31 downto 0). The error I'm…

vhdl modelsim intel-fpga quartus

asked Apr 16 '15 at 18:20

Nate

22,356
31
115
196

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2 answers

modelsim: find processes/variables

I would like to write a nice function that adds signals and process variables to the wave. While it's quite easy with signals, I don't know how to do it with variables. I would expect something like "find processes" and "find variables" in analogy…

vhdl modelsim

asked Nov 18 '13 at 14:25

Andy

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1 answer

Weak 'H', Pullup on inout bidirectional signal in simulation

Is there a way to tell the simulator (I'm using Modelsim) to pull a signal to weak 'H' when it's not being driven by either bidirectional interface? For example if I have an I2C signal I2C_SDA that is declared as an inout from 2 modules. One is…

vhdl modelsim

asked Oct 01 '13 at 13:32

Russell

3,013
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24
44

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0 answers

Scons for FPGA?

Is there somebody who has used 'Scons' as a replacement for 'make' for quite large FPGA projects? Did it ran out-of-the-box or is there still some hacking to be done for the VHDL or Verilog language? And what about the integration with…

vhdl verilog scons fpga modelsim

asked Jan 29 '13 at 08:57

vermaete

1,300
1
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27

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3 answers

Modelsim and GHDL cannot dump vhdl user-defined signal types into vcd?

I'm trying to dump internal signals from a simulation executed either by modelsim or ghdl. Everything works fine using: For modelsim, add vhdl sources, and compile all then: vsim -novopt work.uut_testbench vcd file ../uut.vcd; vcd limit…

signals vhdl modelsim ghdl

asked Mar 11 '12 at 13:02

Tarek Eldeeb

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2 answers

Shifter output is always 0 when using concatenation and case

I have the following code: module shifter( input[7:0] in, input[1:0] amt, output logic[7:0] out ); always_comb case(amt) 2'h0: out = in; 2'h1: out = {{in[6:0]}, 0}; 2'h2: out = {{in[5:0]}, 0, 0}; 2'h3: out = {{in[4:0]},…

verilog system-verilog modelsim intel-fpga

asked Jun 14 '18 at 06:28

jeanluc

1,439
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10
24

votes

1 answer

Cocotb VHDL need for FLI

I am currently setting up a Cocotb based verification environment. I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface). I get the following…

vhdl verilog modelsim intel-fpga cocotb

asked Nov 09 '16 at 16:31

user1654361

votes

2 answers

VHDL - Why does using the length attribute directly on a function produce a warning?

I have a VHDL function that returns a std_logic_vector representation of a record and I want the length of that std_logic_vector. I am able to use the length attribute directly on the function. Why does this produce a warning in ModelSim? Am I…

vhdl modelsim

asked Oct 27 '16 at 00:01

Scott Watson

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1 answer

Using VHDL Record in SystemVerilog Testbench in Modelsim

I've done research on this, but the examples that I've found on other web pages have broken links. I'm looking for an example of how to import a custom VHDL record that is contained in a package into a SystemVerilog Testbench. I'm using modelsim,…

vhdl system-verilog modelsim

asked Feb 08 '16 at 20:38

Russell

3,013
3
24
44

votes

1 answer

Quartus II use file only in simulation

I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component includes statements which are not syntesizeable). My…

vhdl modelsim quartus

asked Jan 16 '16 at 16:36

alabamajack

votes

5 answers

How to wait for Modelsim Simulations to complete before proceeding in TCL script

I am trying to execute a regression test in Modelsim. I call a TCL script which compiles my source files and launches vsim. I launch a .do file and it runs a series of testbenches which all output result files. What I am adding is an automated…

tcl vhdl modelsim

asked Jun 08 '15 at 19:43

jarickc

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1 answer

VHDL integer range inclusive? Difference in FPGA vs. simulation

I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand. I have a 50MHz clock source. I have a signal defined as: SIGNAL ledCounter : integer range 0 to 25000000 := 0; When the ledCounter reaches…

vhdl fpga modelsim intel-fpga

asked Mar 11 '15 at 19:10

RobC

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