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I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here:

...
signal x,y,z : bit;
...
process (y)
begin
  x<=y;
  z<=not x;
end process;

The example says this:

If the signal y changes then an event will be scheduled on x to make it the same as y. Also, an event is scheduled on z to make it the opposite of x. The question is, will the value of z be the opposite of y? Of course, the answer is no, because when the second statement is executed, the event on x has not been processed yet, and the event scheduled on z will be the opposite of the value of x before the process begins.

Well, I need to understand some things:

  1. From what I learned, signals values are updated only at the end of the process. Is this correct?
  2. The signal x is updated as the first statement. This does not still change the value of x, this change is put in a queue to be executed after the process ends. So everything after this statement x <= y will not see the change and will see x having its old value. Is this correct?
  3. The second statement is an attempt to change the value of signal z. The same here, z will not change its value but it depends on the value of another process. The change on z will be put in queue to be executed at the end of the process. Is this correct?

What does happen at the end of the process?

Possibility number 1) The value in x is changed so x has its new value. The second signal z is updated, the first signal x was updated and, given that z depends on x, its value is changed basing on the NEW UPDATED value of x. And the example should work fine.

Possibility number 2) The value in x is changed so x has its new value. The second signal z is updated. Given that z was assigned an old value of x, that's the value that z will hold, the old value of x which was updated, but this update is not considered.

Could you please tell me which one is the correct way?

Étienne
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Andry
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3 Answers3

12

Variables get updated as you assign them. Signals get update in the next delta cycle (at the earliest). 

a := '1'; -- variable
assert a = 1;
b <= '1'; -- signal
computationUsing(b); --reads old value of b
-- new value will be visible after this process ends or some time passes

Jan Decaluwe explains this stuff in more detail here: http://www.sigasi.com/content/vhdls-crown-jewel

rick
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Philippe
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  • Thanks philippe, it's a bit better now but I still do not understand why the example does not work. I mean, The first statement tries to assign to x te value of y. OK this assignment is made at the end of the process so, when I use the signal x again for updating another signal, I do not have the value of that signal. I suppose that all signal handling expressions are kept in a queue so that they are processed at the end of the process. At the end of the process the queue of signal assignment is considered and x is updated and after it, z is updated too.... what am I getting wrong? – Andry Feb 21 '11 at 08:20
  • @Andry The scheduled value of a signal can be overwritten by a sequential signal assignment later in the process. – Jan Decaluwe Feb 21 '11 at 08:24
  • @Jan I'm very sorry Jan but I keep on not understanding. Maybe this argument is difficult to comprehend to me or... I do not know. I just would like to understand why that example is not working, please see my edits. – Andry Feb 21 '11 at 08:52
  • @Andry: what are you not getting? Its what you have outlined in your Possibilty (2) above. z gets its value based on the old value of x because it doesn't see the new value – N.S. Dec 06 '18 at 00:32
7

The way it works:

Y changes and the process begins.

X will be assigned to what Y's value currently is, but not until the end of the process

Z will be assigned to not X's old value but not until the end of the process

The process ends so now X and Z will be updated

WuHoUnited
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  • But... isn't that in sequential statements inside after the begin clause of the architecture????? A process, instead, is just the way we use to create sequential statements... am I correct??? – Andry Feb 20 '11 at 23:00
  • The process itself can be 1 sequential statement in a list of other sequential statements. The things inside the process are not. – WuHoUnited Feb 20 '11 at 23:05
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    Not correct. A process statement itself is a concurrent statement. What it contains are sequential statements, such as variable assignments and sequential signal assignments. – Jan Decaluwe Feb 21 '11 at 08:17
  • Please get a decision because I'm not understanding this very well. I knew from the beginning that EVERYTHING in a process statement is executed sequentially and this was demostrated to me many times that's why I consider this one of the pillars of my knowledge. Please don't destroy this pillar of mine :) – Andry Feb 21 '11 at 08:22
  • @Andry I suggest to decide for yourself who is making sense here. Pick up a good tutorial, or the LRM. Hint: there is a difference between "sequential" and "variable semantics". – Jan Decaluwe Feb 21 '11 at 08:29
0

I disagree with Ashraf's post. I have made vhdl code myself where variables are wires, and signals are latches. Examples:

signal x,y,clk; process(clk) begin x <= y end process

This creates a synchronous latch, a flip flop.

Any variable which does not assign its value to a signal, but only to other variables, is a perfectly acceptable "wire".

My understanding of the whole subject is this:

A signal assignment inside a process will disregard other signal assignments made in the same process "instantiation". Also, for the same signal, only the last assignment will be taken into account.

About "Ok END OF THE PROCESS: What does it happen?????":

I think that a signal assignment will take place at the fastest possible time the hardware utilization of the process allows. EXCEPTION: Changes within a if(rising_edge(clk)) will take place at the start of the next clock cycle.

user1058795
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  • EXCEPTION: is incorrect. Changes within `if rising_edge(clk)` take place in time for the NEXT DELTA CYCLE after the clk edge. However they are only SEEN by the clocked process on the next clock cycle. – user_1818839 Sep 29 '13 at 12:42