I'm trying to create a very simple watch (I don't use the word "clock" to avoid misunderstandings) on my FPGA (it displays seconds, minutes and hours) for an assignment and a friend of mine gave me some code that actually works when I synthesize it on my FPGA, but I can't understand why. Here's the main process.
main: process(clk)
begin
if((clk='1' and clk'event) and en='1') then
if(init = '0') then
sec <= conv_integer(seconds_in);
min <= conv_integer(minutes_in);
hour <= conv_integer(hours_in);
init <= '1';
else
count <= count + 1;
if(count = 1000000) then
sec <= sec+1;
count <= 0;
if(sec=59) then
min <= min+1;
sec <= 0;
if(min=59) then
hour <= hour+1;
min <= 0;
if(hour=23) then
hour <= 0;
count <= 0;
end if;
end if;
end if;
end if;
end if;
end if;
end process main;
It starts by initializing the integers sec
, min
and hour
to the initial value set by the user. Then, it does the actual work of incrementing the variables every second, minute or hour. The frequency of clk
is 1 MHz.
Reading the code, it seems that hour
(for istance) should increment just after min
turns to 59, without waiting a full minute. But, when I synthesize it on the FPGA, it works fine, just as you would expect. Unfortunately, I can't run a simulation. Maybe this has something to do with the scheduling of the process? I'm still a beginner and maybe I'm missing something.
[EDIT]
Thanks to the comments, I noticed a small error in the code above (count
was not correctly reset). Fixed it!