Stack Overflow
Stack Overflow

Questions tagged [vhdl]

VHDL (VHSIC Hardware Description Language) is a language used in electronic design to describe digital systems such as FPGA (field-programmable gate arrays) and IC (integrated circuits).

A hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays (FPGAs) and integrated circuits (ICs). VHDL can also be used as a general-purpose parallel programming language

When asking a question, please specify whether you are looking for a synthesizable solution or one for a testbench.

The Wikipedia page says:

VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.

VHDL is standardized as IEEE 1076-2008 (non-free download).

5482 questions
1
vote
3 answers

Problem with net instantiation

I have a very simple statemachine that sets some control signals to interact with a third party IP. The code looks roughly as follows: entity testip is port ( ... fifo_dataout : in std_logic_vector(0 to 31); ip_dataout :…
Richard29
  • 31
  • 1
  • 3
1
vote
0 answers

Modelsim error "is not an operator symbol"

I wrote code, but ModelSim said : "unsigned2hexstring" is not an operator symbol. What should I change and how use mine package like library? Is it will like : library ieee; use ieee.std_logic_1164.all; use work.prosoft_std.all ??? library…
Nikita Malyshev
  • 67
  • 5
1
vote
0 answers

Resetting an IP Core FIFO in Modelsim

I'm using the builtin FIFO, in FWFT mode. I try resetting it for 9 clocks, then leave the reset line low at the beginning. There is a large gap before the first write enable rises. Modelsim then complains that I have not reset the FIFO correctly…
fiz
  • 862
  • 2
  • 12
  • 35
1
vote
1 answer

Best and Fastest Way for adding two std_logic_vector in VHDL

In VHDL if I have a STD_LOGIC_VECTOR as per following declaration: signal RAM_ADDR : STD_LOGIC_VECTOR (2 downto 0) := (others => '0'); If I try to increment this address in a loop with the '+' operator as per following: for i in 0 to 7 loop …
pittuzzo
  • 452
  • 6
  • 23
1
vote
0 answers

VHDL code error 211 modelsim shifter

library ieee; use ieee.std_logic_1164.all; --use ieee.numeric_std.all; entity shifter is port(inputt:in std_logic_vector (7 downto 0); shiftextent:in integer ; outt :OUT STD_LOGIC_VECTOR(15 downto 0)); end shifter; architecture…
Jack
  • 21
  • 4
1
vote
1 answer

How to use an entity inside an architecture in VHDL

My purpose is to impement a Keyboard entity which uses Button entites. So I wrote the following VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Keyboard is port ( ck, stop : in STD_LOGIC; data_in : in…
pittuzzo
  • 452
  • 6
  • 23
1
vote
1 answer

ALU design error

I want to design an 8 bit alu in VHDL but I get this errors, I think it has something to do with the fact that my inputs are declared as bit_vectors. Is that true? ** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(19): No feasible…
blaa
  • 761
  • 2
  • 15
  • 30
1
vote
0 answers

Documente inside a vhdl process with doxygen

I'm documenting my VHDL project with doxygen. I have a problem when I try to documentate the statements inside a process. If I try with "--!" the comment doesn't appear in doxygen HTML output. Can statements inside a process (if, when... case) be…
ferdepe
  • 456
  • 4
  • 19
1
vote
0 answers

Unassigned outputs in VHDL simulation

I've been having problems while simulating a code in VHDL in ModelSim, the purpose of the code was to make a sum and a subtraction of two numbers, represented as vectors and store the results in two another vectors. But, when I start the simulation,…
Gabriel Gonçalves
  • 11
  • 2
1
vote
1 answer

VHDL Delay before lighting led

I want to make a simple vhdl code which makes a delay of 20 sec before a led will be ON. i used a signal counter to make the delay of the 20 sec, but i've noticed to very strange thing, if i am not declare that the led is OFF before the delay, the…
tomerJK
  • 39
  • 7
1
vote
0 answers

signal declaration using with generate statement

How can i declare a series of signal using generate statement in VHDL? i use generate statement but i can't compile code because of errer. architecture DATAFLOW of P_2 is signal L3_0 : std_logic ; signal L3_1 : std_logic ; signal L3_2 : std_logic…
ali.329
  • 11
  • 1
  • 5
1
vote
2 answers

VHDL ATTRIBUTE keep

I am currently studying VHDL about SR Latch, and there comes to a part which I don't understand. Can anyone explain What does ATTRIBUTE keep: boolean mean and what does it do in VHDL? Thank you.
samheihey
  • 133
  • 2
  • 13
1
vote
1 answer

VHDL Synthesis, can`t make code be synthesizable

I have some code on VHDL language, this code male some encryption/decryption operation. Help me please make this code be synthesizable because Xilinx IDE told me that line 82: Operator must have constant modulo operand. This is my code. Maybe…
Nazar
  • 11
  • 2
1
vote
1 answer

Where to put a .txt file if I want to read it out from the integrated Simulator in Vivado?

I have a text-file I want to read in inside my simulation.vhd file but I do not know where to put it so that the code finds it, since I am not quite sure where it gets executed.
Kev1n91
  • 2,867
  • 5
  • 36
  • 73
1
vote
1 answer

Compile Vivado IP-generated Librarys in ".ip_user_files" for ModelSim on Win7

thanks for reading my question. If i generate a component with the "IP Catalog" in Vivado (2016.2), Vivado creates the following Folder(s) in my Project (I generated a counter for this…
iicud
  • 19
  • 3
1 2 3
…
99
100