Stack Overflow
Stack Overflow

Questions tagged [cortex-a]

For all ARM cortex-A series CPUs, including A5,A7,A8,A9 and A15.

Please use this tag instead of other specific Cortex-A tags See: Merge ARM tags.

This tag is for questions related to the ARM cortex-A microcontrollers, also known as the ARMv7A. It is the 7th generation of ARM CPUs. Other variants are the Cortex-M and Cortex-R. The Cortex-A (application) is generally the most complex of the group.

Members of the Cortex-A family are very similar except for CPU pipeline and some optional instructions. Only very details system information will differ (like co-processor 15 registers). However, even within the same model (Ie, a cortex-A8 from two different vendors) these details may vary.

See also:

Specific ARM literature to Cortex-A CPUs,

132 questions
39
votes
1 answer

Measurement of TLB effects on a Cortex-A9

After reading the following paper https://people.freebsd.org/~lstewart/articles/cpumemory.pdf ("What every programmer should know about memory") I wanted to try one of the author's test, that is, measuring the effects of TLB on the final execution…
D4l3k
  • 575
  • 3
  • 13
16
votes
4 answers

ARM: Start/Wakeup/Bringup the other CPU cores/APs and pass execution start address?

I've been banging my head with this for the last 3-4 days and I can't find a DECENT explanatory documentation (from ARM or unofficial) to help me. I've got an ODROID-XU board (big.LITTLE 2 x Cortex-A15 + 2 x Cortex-A7) board and I'm trying to…
Zuzu Corneliu
  • 1,286
  • 12
  • 23
7
votes
2 answers

cortex a9 boot and memory

I am a newbie starting out in micro-controller programming. The chip of interest here is cortex-a9. At reset or power up there has to be code at 0x0000000 from my readings. My questions though they may sound too trivial will help me in putting some…
Tony Prasad
  • 71
  • 2
  • 3
6
votes
1 answer

Domain in arm architecture means what

When I debug MMU in Cortex-A9 MPCore, I always see Domain Access Control Register, but, what does domain means ? up to 16 domains ? Anyone can give me a link to explain this ?
kavin zhuang
  • 65
  • 7
6
votes
2 answers

L1 cache ports in ARM Cortex processors

I did some reseach, but could not find much information. I'd like to know how many L1 read and L1 write ports ARM embedded processors have and how wide the ports are. Specifically, I am interested in Cortex-A8, Cortex-A9, and Cortext-A15. My blind…
aminfar
  • 2,067
  • 3
  • 23
  • 37
5
votes
3 answers

ARM Thumb mode: Code Size not decreasing

Guys, I have a project which I have compiled for the ARM Cortex-A8 processor. I'm making use of GCC to do this. Currently the size of my executable is 220.1 KB. Now I modify my makefile and I add the flag -mthumb, the makefile line looks somewhat…
HaggarTheHorrible
  • 6,335
  • 16
  • 63
  • 79
5
votes
5 answers

Load 8bit uint8_t as uint32_t?

my image processing project works with grayscale images. I have ARM Cortex-A8 processor platform. I want to make use of the NEON. I have a grayscale image( consider the example below) and in my alogorithm, I have to add only the columns. How can I…
HaggarTheHorrible
  • 6,335
  • 16
  • 63
  • 79
5
votes
2 answers

Read-only file-system on yocto

i have a few questions about the "read-only-rootfs" feature from the yocto project, the documentation is not that helpful unfortunately. So adding that to the EXTRA_IMAGE_FEATURES makes the yocto fs read only, but in: 5.15.3. Areas With Write…
Mihai
  • 760
  • 9
  • 30
5
votes
2 answers

PoU and PoC in cache maintenance operations in arm

When reading ARM arch. ref. manual v7, I've found two concepts; point of coherency (PoC) and point of unification (PoU). For PoC, it looks like the point that all agents (i.e., CPU cores) can see the same copy of memory. For PoU, it looks like the…
jaeyong
  • 7,966
  • 10
  • 44
  • 56
4
votes
1 answer

Reading Armv8-A registers with devmem from GNU/Linux shell

I want to read the values of some Cortex-A53 registers, such as D_AA64ISAR0_EL1 (AArch64) ID_ISAR5 (Aarch32) ID_ISAR5_EL1 (Aarch64) Unfortunately, I lack a little embedded/assembly experience. The documentation reveals To access the…
smoothware
  • 756
  • 5
  • 15
4
votes
3 answers

TrustZone of the Cortex-M23/33 vs. TrustZone of the Cortex-A

What is the difference between the TrustZone of Cortex M23/33 and the TrustZone of Cortex A? May I start to prototype my Cortex M23 application on a Cortex A processor and then migrate to Cortex M23 when chips with this core are available?
Stefan
  • 63
  • 7
4
votes
0 answers

Aligning a .data or .text section

I am building a bootloader for an ARM Cortex-A9 target. The output of the Microsoft linker is passed to a locator application (romimage) that locates the linker output section and builds the linear memory layout that runs in the target. One part of…
harper
  • 12,491
  • 6
  • 49
  • 95
4
votes
0 answers

Incorrect return address is POPed after SVC call

I am working on an ARM Cortex-A5 core of a custom processor and getting a really weird issue which seem to be unexplainable from the SW point of view. The issue is that at some point when stress-testing the system (rebooting hundreds of times),…
Eugene Sh.
  • 16,386
  • 4
  • 33
  • 51
4
votes
0 answers

node js for Arm cortex a5

I have an issue with cross compiling node.js to Cortex A5 target please guide me I have an Atmel SAMA5D31-ek , running linux on it. Below is the CPU information >cat /proc/cpuinfo processor : 0 model name : ARMv7 Processor rev 1 (v7l) Features …
raghunandana SP
  • 41
  • 3
3
votes
1 answer

Zynq 7000: Minimum asm code to init cpu1 from cpu0

I'm trying to figure out the minimum requirements to initialize cpu1 from cpu0 in an amp configuration on a zynq-7000. I have a given FSBL that hands over to u-boot with which I copy both programs (cpu0/1) from flash to different locations in ram…
robsn
  • 700
  • 4
  • 17
1
2 3
…
8 9