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Questions tagged [cortex-a]

For all ARM cortex-A series CPUs, including A5,A7,A8,A9 and A15.

Please use this tag instead of other specific Cortex-A tags See: Merge ARM tags.

This tag is for questions related to the ARM cortex-A microcontrollers, also known as the ARMv7A. It is the 7th generation of ARM CPUs. Other variants are the Cortex-M and Cortex-R. The Cortex-A (application) is generally the most complex of the group.

Members of the Cortex-A family are very similar except for CPU pipeline and some optional instructions. Only very details system information will differ (like co-processor 15 registers). However, even within the same model (Ie, a cortex-A8 from two different vendors) these details may vary.

See also:

Specific ARM literature to Cortex-A CPUs,

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How to understand why an ARM exception happens?

I'm trying understand what is the reason of ARM exception that I encounter. It happens randomly during system startup, and may looks in few different ways. One of simplest is following: 0x8004e810 in ti_sysbios_family_arm_a8_intcps_Hwi_vectors () #0…
wiesniak
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Logging and debugging unaligned accesses on Linux / aarch64

How can I log unaligned memory accesses on Linux / aarch64 (Cortex-a57)? I understand there are two different things involved here: Choosing to raise an interrupt from the cpu on an unaligned access (ie. interrupts for unaligned memory accesses…
Florian Castellane
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Cache timing on ARM processor

i need to implement AES algorithm on a smartphone with ARM Cortex A-15 processor(Samsung Galaxy Note 3, etc) and need to observe and save cache timings for each process, round. How do I go about it? To be precise, I need to observe time taken by the…
Tashi
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How to divide the L2 cache between the cores on a ARM Cortex-A7?

Context and goal I'd like to run two fully standalone applications on my Olimex A20 Lime platform that run a ARM Cortex-A7. The goal is to dedicate one core to each application. So far so good. Now I'd like to divide the L2 cache between the cores…
cid
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what does this ARM instruction asm("b .\n"); mean?

the following code is seen in reset handler: asm("b .\n"); This is arm for processor. Can someone explain this?
kiran bobbu
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Arm cortex a9 memory access

I want to know the sequence an ARM core (Cortex-A series processor) accesses memory? Right from Virtual Address generated by core to memory and Instruction/Data transferred from the memory to the core. Consider core has generated a virtual address…
Ganesh Kalbhor
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Why is the reset handler located at 0x0 for Cortex-A but not for Cortex-M3

What is the reason Cortex-M3 has the initial stack pointer value located at 0x0, and reset handler located at 0x4? What is the design justification for this? Why couldn't the ARM guys leave 0x0 to the reset handler like they do for Cortex-A, then…
neuron
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Send Inter-Processor Interrupts in Zynq (arm-v7 / cortex-a9)

I am trying to add multiprocessor support for an embedded operating system (DNA-OS) on the Zynq platform in the ZedBoard. The OS is actually flawlessly functional with CPU_0 alone. The OS architecture requires the implementation of a cpu_send_ipi…
Younes Regaieg
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ARM single-copy atomicity

I am currently wading through the ARM architecture manual for the ARMv7 core. In chapter A3.5.3 about atomicity of memory accesses, it states: If a single-copy atomic load overlaps a single-copy atomic store and for any of the overlapping bytes…
Vroomfondel
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Getting zeros on Cortex-A9 PMU counters

not sure if this the right place to ask but i really need help. I am attempting to gather some data on Galaxy Nexus i9250 Android v4.3 CPU ARMv7.I am trying to use ARM Streamline but it provides the following error: ARM Processor PMU event counters…
user2320492
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Why cache misses happen more when more data is prefetched on ARM?

I'm using OProfile to profile the following function on a raspberry pi 3B+. (I'm using gcc version 10.2 on the raspberry (not doing cross-compilation) and the following flags for the compiler: -O1 -mfpu-neon -mneon-for-64bits. The generate assembly…
Da Teng
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How to debug TF-A on ARM Cortex-A7

I'm trying a custom image for ARM STM32MP151A on a custom board. On power up nothing happens on the tty port (while using a wrong sd-card leads to a PANIC PC error - hence the port is ok). As far as I understand in the early stages of power up…
Mark
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Cortex-A8 out-of-order execution and Spectre

I am reading about ARM Cortex-A8 processor and found that this processor does not support out-of-order execution. However, in https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability Arm clarified that Cortex-A8 is…
alireza sadeghpour
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no effect of PLD in cortex A9

I am using the following program to check the effect of PLD on performance. However, I couldn't find the difference in performance with and without PLD the C code I've written. Is there anything I am missing or any compiler option I need to add? int…
raaj
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usage of PLD in arm cortex a9

I am trying to use PLD instruction. The problem I am facing is as follows: int32_t addr[10]; asm ("PLD [addr,#5]"); I am getting following error: Error: ARM register expected -- `pld [addr,#5]'
raaj
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