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I'm using Verilog for a design and am using an integer that gets re-defined every time the always block runs at the positive clock edge. This works fine for one of my two arrays in the always block, but Vivado complains about (only) the second array that uses a "non-constant" for the index for selecting a slice of the array. o_pl_inst is a 128-bit register, and csh_reg is a 128-megabit register, of which I'm selecting 128 bits at a time to store in o_pl_inst. How is it that in the same situation, I'm having no issues with assigning to a dynamic slice of an array, as in "csh_reg[i*i-127] = activ_inst;" but I can't get a value in the same manor? Any assistance would be greatly appreciated.

I've tried moving my array declarations to outside of the always block, but that caused new issues.

    always@(posedge clk) begin
            // Load instructions into the CSH
            int i = (inst_width*(sp_csh+1))-1; /*Reference index generation for dynamic array slicing*/
            int j = (i_pl_sp*128)-1; /*Reference index generation for dynamic array slicing*/

            csh_reg[i*i-127] = activ_inst; /*Load 128-bit instructions into the array 128 bits apart*/
            sp_csh = sp_csh +1; /*Increment internal CSH_sp*/
            activ_inst = i_ps_inst; /*Get next instruction*/

            // Save instruction from CSH
            o_pl_inst = csh_reg[j:j-127]; /*Retrieve 128-bit instruction from 1 of 1048576 positions in CSH*/
    end

I need the fix/alternative to be synthesizable. From what I've read, Vivado tends to have issues with using a non-constant be using to slice an array, but it's only happened with the second array...

Adhamzhon Shukurov
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user2996871
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    A 128 _megabit_ register? What hardware are you targeting? The Xilinx UltraScale+ series tops out around 48 Mbit of distributed RAM. – duskwuff -inactive- Jan 17 '19 at 02:22
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    how did you define it? you are assigning a single array element (?) or a bit? you reading a range. There is a difference. But you need to provide your declarations of csh_reg and other vars. Also, which language are you targeting? there is no 'int' in verilog. Also, for variables if you use `i * i` you are implementing a multiplier. – Serge Jan 17 '19 at 03:17
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    If you want to select a dynamic slice, but of a fixed size, check out the indexed part select: https://stackoverflow.com/q/17778418/1253433 – dwikle Jan 17 '19 at 04:33
  • After you have looked at all that: fix you assignments: use non-blocking in a clocked section. – Oldfart Jan 17 '19 at 07:54
  • Addressing the first comment: My understanding was that each block RAM was 32kb, and that there were over a thousand BRAMs in my chip, but I now realize there are only 895 which is equal to roughly 28 mega bits. That's fine, I can adjust for that. 3Mb of cache is fine. Second comment: How was it defined? it's defined as such- reg csh_reg [inst_cnt*inst_width-1:0]; Where inst_cnt is now defined as- parameter inst_cnt = 212992; (This cuts from 128Mbit to 27.2Mbit to accommodate the suggestions of comment 1). Finally, using non-blocking statements didn't change the errors in this case. – user2996871 Jan 17 '19 at 13:19
  • Also, I followed the link in the third comment, and that reduced the number of issues Vivado had with that line from 3 or 4, down to 1, so thank you! Now it just complains that I'm assigning an unpacked type to a packed type. – user2996871 Jan 17 '19 at 13:23

1 Answers1

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The issue has been resolved thanks largely to the comments. I will share what was changed to get it to function; First, my BRAM usage was too high. Obviously before attempting synthesis I wasn't getting any warnings about that, but I would've run into it either during synthesis or implementation, so I adjusted that in accordance with my chip's datasheet to not use more than the available BRAM. Second, I was using a form of dynamic slicing that wasn't supported in Vivado, but was supported in other tools such as Quartus, so I changed that using the link shared in the comment by @dwikle. After that I was left with an error that was just a silly mistake on my part in my declaration: I had declared one of my parameters as a vector, and tried to assign it to an array. So I changed that. Thanks everyone.

user2996871
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