error reports on v 53,55,57 it says module instantiation should have an instance name how can I solve this problem?
my_adder is 32 bit adder, it's overflow is 1 bit. but overflow in adder_array is 4 bit. how can I solve this?
module adder_array(
cmd,
ain0, ain1, ain2, ain3,
bin0, bin1, bin2, bin3,
dout0, dout1, dout2, dout3,
overflow);
input [2:0] cmd;
input [31:0] ain0, ain1, ain2, ain3;
input [31:0] bin0, bin1, bin2, bin3;
output reg [31:0] dout0, dout1, dout2, dout3;
output [3:0] overflow;
wire [31:0] a[3:0];
wire [31:0] b[3:0];
wire [31:0] d[3:0];
wire ovf[3:0];
assign {a[0],a[1],a[2],a[3]} = {ain0,ain1,ain2,ain3};
assign {b[0],b[1],b[2],b[3]} = {bin0,bin1,bin2,bin3};
assign {d[0],d[1],d[2],d[3]} = {dout0, dout1, dout2, dout3};
parameter size = 4;
genvar i;
generate for(i = 0 ; i < size - 1 ; i = i + 1)
begin: adder
if (i == 0) begin
my_add(.ain(a[0]), .bin(b[0]), .dout(d[0]), .overflow(ovf[0]));
end
else if (i == size - 1 ) begin
my_add(.ain(a[i]), .bin(b[i]), .dout(d[i]), .overflow(ovf[i]));
end
else begin
my_add(.ain(a[i]), .bin(b[i]), .dout(d[i]), .overflow(ovf[i]));
end
end
endgenerate
assign overflow = {ovf[3], ovf[2], ovf[1], ovf[0]};
always @(cmd) begin
case(cmd)
3'b000 : begin dout0 = d[0]; dout1 = 0; dout2 = 0; dout3 = 0; end
3'b001 : begin dout0 = 0; dout1 = d[1]; dout2 = 0; dout3 = 0; end
3'b010 : begin dout0 = 0; dout1 = 0; dout2 = d[2]; dout3 = 0; end
3'b011 : begin dout0 = 0; dout1 = 0; dout2 = 0; dout3 = d[3]; end
3'b100 : begin dout0 = d[0]; dout1 = d[1]; dout2 = d[2]; dout3 = d[3]; end
endcase
end
endmodule