I'm trying to write some fairly generic VHDL code but I'm running into a situation where I don't understand the standard well enough. (I'm using VHDL-2008.)
I have written a function that operates on unconstrained std_logic_vector(s) and returns an unconstrained std_logic_vector. However, it seems as if I am unable to use this function as an input to a port in my entity if I pass two (constrained) std_logic_vectors to it (see instantiation of test_2 in my example program). However, for some reason it seems to work ok if I pass bit string literals to it (see instantiation of test_1).
Can someone explain why the I am not allowed to use the concatenate() function as an input in the instantiation of test_2 while I am allowed to use a very similar construct in the instantiation of test_1?
To try the code with ModelSim I compiled it with vcom -2008 unconstrained_example.vhd
-- test entity/architecture
library ieee;
use ieee.std_logic_1164.all;
entity test is
port (value : in std_logic_vector);
end entity;
architecture a of test is
begin
-- Intentionally empty
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- Test instantiation
entity testit is
end entity;
architecture a of testit is
signal my_constrained_slv1 : std_logic_vector(5 downto 0);
signal my_constrained_slv2 : std_logic_vector(9 downto 0);
function concatenate(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is
begin
return value1 & value2;
end function;
begin
process begin
-- Using the function in this context seems to work ok
report "Value is " & to_string(concatenate(my_constrained_slv1, my_constrained_slv2));
wait;
end process;
-- This instantiation seems to work
test_1: entity work.test
port map (
value => concatenate("000000", "1111111111"));
-- For this entity instantiation I'm getting an error from ModelSim:
-- ** Error: unconstrained_example.vhd(43): (vcom-1383) Implicit signal in port map for port "value" is not fully constrained.
test_2: entity work.test
port map (
value => concatenate(my_constrained_slv1, my_constrained_slv2));
end architecture;