Hey guys so I written two Verilog modules, one is a state machine and the other is a counter that generates a pulse every half second for the machine to count.I tried to make a a top level design that would instantiate both modules, however when running a test bench, my state outputs would always equal to 'xx'. Any advice or help please?
COUNTER/PULSE:
module pulseit(clk, reset, pulse);
input clk, reset;
output pulse;
reg [25:0] count;
wire pulse;
always @ (posedge clk, posedge reset)
if (reset) count <= 26'b0; else
if (pulse) count <= 26'b0; else
count <= count + 26'b1;
endmodule
STATE MACHINE:
module sm(clk, reset, in, state, pulse);
input clk, reset, in, pulse;
output [1:0] state;
reg [1:0] state, nstate;
always @ (posedge clk, posedge reset)
if (reset) state <= 2'b0;
else state <= nstate;
always @ (*)
begin
nstate = state;
if (pulse)
begin
case(state)
2'b00: nstate = (in)? 2'b01:2'b11;
2'b01: nstate = (in)? 2'b10:2'b00;
2'b10: nstate = (in)? 2'b11:2'b01;
2'b11: nstate = (in)? 2'b00:2'b10;
endcase
end
end
endmodule
TOPLEVEL:
module topLevel(clk, rst, in, state);
input clk, rst, in;
output [1:0] state;
reg [1:0] state;
wire y;
pulseit pull (.clk(clk), .reset(rst), .pulse(y));
sm machine (.clk(clk), .reset(rst), .in(in), .state(state), .pulse(y));
endmodule