In systemverilog is there a way to condition on a type?

Question

So I am using a parameterized type in a common module.

Is there a way to say: if( type == TYPE1 ) assign the struct one way else if( type == TYPE2 ) assign another way

I was picturing this in a generate block.

Answer 1

Yes, you can use the type operator do a generate-if/case, or procedural if/case like:

real r;

if ( type(r) == type(real) ) ...

But unfortunately the code in all branches still must successfully compile, regardless of the condition. You will not be able to reference struct member that does not exist.

  typedef struct {int a;} s1_t;
  typedef struct {int a;int b;} s2_t;
  s1_t s;
 initial
      #1 // procedural-if
    if (type(s) == type(s1_t))
      $display("%m s.a = %0d",s.a);
    else if (type(s) == type(s2_t))
      $display("%m s.b ==%0d",s.b); // this will not compile 

Answer 2

There is type() operator described in IEEE1800-2012 § 6.23. Example usage from from the LRM:

bit[12:0] A_bus, B_bus;
parameter typebus_t = type(A_bus);
generate
  case(type(bus_t))
    type(bit[12:0]): addfixed_int #(bus_t) (A_bus,B_bus);
    type(real): add_float #(type(A_bus)) (A_bus,B_bus);
  endcase
endgenerate

There is also $typename() described in IEEE1800-2012 § 20.6.1. $typename() return s string of the type. Example usage from from the LRM:

// source code            // $typename would return
typedef bitnode;          // "bit"
node [2:0] X;             // "bit [2:0]"
int signedY;              // "int"
packageA;
enum{A,B,C=99} X;         // "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::e$1"
typedef bit[9:1'b1] word; // "A::bit[9:1]" 
endpackage: A
importA::*;
moduletop;
typedef struct{node A,B;} AB_t;
AB_t AB[10];              // "struct{bit A;bit B;}top.AB_t$[0:9]"
...
endmodule