Is it written in VHDL or Verilog

Question

I am new to HDL and just wanted to confirm whether these lines of code are written in VHDL or Verilog?

DE0_SOPC DE0_SOPC_inst(
                        // 1) global signals:
                         .clk(CLOCK_50),
                         .pll_cpu(),
                         .pll_sdram(DRAM_CLK),
                         .reset_n(system_reset_n));

A bit short to make a real guess, and I have only briefly touched VHDL, but this doesn't look like it. — Daniel Jour, Feb 24 '16 at 12:55
I think its Verilog. See [this question link](http://stackoverflow.com/questions/20066850/verilog-how-to-instantiate-a-module). — sharvil111, Feb 24 '16 at 13:00
The file name it is contained in might have a clue, Verilog tends to end with a `*.v` — Morgan, Feb 24 '16 at 13:18
yes, it ends with .v extension. What extension is used for VHDL files then? thank you — Tom, Feb 24 '16 at 13:25
The file extension used for VHDL files is usually `.vhd` or `.vhdl`. But, it is not a requirement. — Martin Zabel, Feb 24 '16 at 14:49
The `//` comment is a dead giveaway. Verilog is based on C syntax; VHDL is based on Ada (VHDL comments are `--`). — callyalater, Mar 01 '16 at 22:19

score 2 · Answer 1 · answered Feb 24 '16 at 13:45

2

It's Verilog. It is an instantiation of a module inside another. This is how you do it in Verilog; it is not how you do it in VHDL.

answered Feb 24 '16 at 13:45

Matthew Taylor

12,111
3
12
39

score 0 · Accepted Answer · answered Feb 25 '16 at 05:52

0

Yes. These are verilog code lines. As per your previous comments, Type: .v files belong to verilog codes.

answered Feb 25 '16 at 05:52

Satheesh.R

49
4

Is it written in VHDL or Verilog

2 Answers2