how to index a reg or memory in for-loop by for-variable?

Question

I have a problem with the code below. The code is synthesized in ISE 14.2.

input [1:8176] m_d_in;
reg [1:511] m_d [1:16];
integer i;

always @ (*)
  begin
    for (i=0; i<16; i=i+1)
       begin
         m_d[i+1] = m_d_in[ 1+511*i : 511+511*i];
       end
  end

after synthesizing, this error shows up:
HDL Compiler:1660_<'Address of CodeName.v> <'Line of Error>: procedural assignment to a non-register i is not permitted, left-hand side should be reg/integer/time/genvar
the line of Error refer to this:

   m_d[i+1] = m_d_in[ 1+511*i : 511+511*i];

i also have tested using the:

reg [4:0] i;

and

genvar i;

instead of:

integer i;

and got exactly the same error I wrote above!
I know there is a solution by using a case instead of the code above, but in its not the right solution for me.
Thanks a lot.

Answer 1

Since you are range is consistent, Indexing vectors and arrays with +: is also possible:

always @* begin
  for (i=0; i<16; i=i+1)
    m_d[i+1] = m_d_in[511*i+1 +: 511];
end

The indexed part select (+:/-:) and generate block (from Morgan's answer) were introduced in IEEE std 1364-2001. Any modern simulator and synthesizer will support them.

Answer 2

If you use wire instead of reg then a single assign line can be wrapped up in a generate.

module tb(
input [1:8176] m_d_in
);
wire [1:511] m_d [1:16];

genvar i;

generate
  for (i=0; i<16; i=i+1) begin
    assign m_d[i+1] = m_d_in[ 1+511*i : 511+511*i];
  end
endgenerate

endmodule

To keep the reg and use generates you would need to do:

module tb(
input [1:8176] m_d_in
);
reg[1:511] m_d [1:16];

 genvar i;

generate
  for (i=0; i<16; i=i+1) begin
    always @* begin
      m_d[i+1] = m_d_in[ 1+511*i : 511+511*i];
    end
  end
endgenerate

endmodule