verilog-what this statement is doing "+:"

Question

The code given below is converting a multi-dimension array into a single dimension array to give it as output of a module.

1) My question is what is +: is doing in the statement made bold.
2) If we want to make it general, which term in loop is row and which one is column?

module module1(instructionmem);
  output [32*32-1:0] instructionmem;
  reg    [31:0]      instructionmem_array [31:0];

  genvar i;
  generate for (i = 0; i < 32; i = i+1) begin:instmem
     **assign instructionmem[32*i +: 32] = instructionmem_array[i];** 
  end endgenerate
endmodule

Answer 1

The +: syntax is used for reading and writing variable slices of an array.
The main syntax is a = b[offset +: fixed_width], which is equivalent to:

a = b[offset : offset + fixed_width];

It is worth noting that the above is not synthesizable due to the possibility that you may have included a dynamic width. The new syntax using +: was introduced to get around that issue and is synthesisable.

This is covered in section 11.5.1 Vector bit-select and part-select addressing of SystemVerilog IEEE 1800-2012.

---

To define a 32 bit word we can do:

reg [31:0] a_word; 

To turn this into a 32 bit wide, 10 locations deep memory (multi dimensional array), as per your question we can do:

reg [31:0] a_memory [0:9]; 

When accessing a locations the first [] change from accessing bits of a word, to word from the memory. ie

initial begin 
  a_bit  = a_word[31];

  a_word = a_memory[9];

  a_bit  = a_memory[9][31];
end

Memories are covered in Section 7.4.4 of SystemVerilog IEEE 1800-2012.