I have a case structure in Verilog with approximately 95 cases.
case(address)
5'd0: header_buffer[7:0] <= writedata;
5'd1: header_buffer[15:8] <= writedata;
5'd2: header_buffer[23:16] <= writedata;
5'd3: header_buffer[31:24] <= writedata;
As you can see, there is a very predictable pattern. Is there a better way to write this so that I don't have to manually write out all of the cases and so that I can scale it to an arbitrarily large size such as 100 or 200 cases? It seems like some type of for loop syntax would be very useful.