I am just starting to learn verilog, so this may be a very basic question, but i couldn't really understand or find an alternative to express my intentions in verilog.
I will take a smaller example. I am basically trying to connect the output of one of my modules to input for another. Please help me with line mark 49 and give an alternative to it.
25 module ands (
26 input1,
27 input2,
28 outputs
29 );
30 input [2:0] input1;
31 input input2;
32 output [2:0] outputs;
33
34 integer itr;
35
36 and a (outputs[0],input1[0],input2);
37 initial
38 begin
39 for (itr = 1 ; itr <= 2; itr = itr+1)
40 and a(outputs[itr],input1[itr],outputs[itr-1]);
41 end
42
43 endmodule
I know it is a stupid example and i can easily avoid using the for loop, but i want to actually later use parameters.
Thanks, and sorry if it is just too basic.