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Questions tagged [riscv32]

41 questions
4
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1 answer

s-files generated from riscv-gnu-toolchain does not run RISCV emulator

I must compile a set of C++ files into RISC-V code (RV32IM). I am using riscv-gnu-toolchain and compiles with the following CMakeLists.txt file cmake_minimum_required(VERSION 3.10.2) project(project-title) set(CMAKE_CXX_FLAGS "-march=rv32im…
eirikvaa
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2 answers

RISCV: how the branch intstructions are calculated?

I am trying to understand how modern CPU works. I am focused on RISC-V. there are few types of branches: BEQ BNE BLT BGE BLTU BGEU I use a venus simulator to test this and also i am trying to simulate it as well and so far so good it works, but i…
Kralik_011
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2 answers

riscv-gcc Fails to build [GCC_NO_EXECUTABLES]

I want to use riscv-gcc to implement an Ibex (RISCV core) example on an Arty-A7 but I haven't been able to build it properly. It's been failing after the 'make' phase. It seems to have something to do with zlib however I'm not so sure since this…
ajabanto
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1 answer

Executing dynamically generated code on RISC-V

I am writing a Forth-like language for RISC-V and naturally that means I need to have a way to allow the users to define new words and execute them. But I am struggling to find a way that will allow users to execute dynamically generated code…
adrianmcmenamin
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2 answers

What does "not" mean in Assembly-RiscV?

What does not mean in RiscV? I got it after translating some code from C like this: not a0, t1
daniel_smith
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1 answer

How do I store or load by byte unit into memory when using “riscv32-unknown-elf-gcc”?

I want to operate memory load or store in BYTE (8-bit) or HALF WORD (16-bit) unit. So I made the C code as below and compiled it using "riscv32-unknown-elf-gcc". void fun3 (void) { char i,j; i = (char)*(volatile unsigned int *) 0xf10007f8; …
doldooly
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1 answer

Access rights in RISC-V linkerscripts

When programming ARM-based microcontrollers, I'm used to see a MEMORY{..} segment in the linkerscript like this: MEMORY { FLASH (rx): ORIGIN = 0x08000000, LENGTH = 128K RAM (xrw): ORIGIN = 0x20000000, LENGTH = 32K } The access rights are…
K.Mulier
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What is intended/correct way to handle interrupts and use the WFI risc-v cpu instruction?

I am very new to bare metal programming and have never delt with interrupts before, but I've been learning on a RISC-V FE310-G002 SOC powered dev board. I've been reading about the RISC-V WFI (Wait for interrupt) instruction and from the manuals, it…
Echelon X-Ray
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1 answer

How is the 34 bit physical address space accessed in a RISC-V 32 bit system when virtual memory is disabled?

In the RISC-V 32 bit ISA, the physical address space is 34 bit with a 32 bit virtual address space. When virtual memory is enabled in supervisor mode the 32 bit virtual address is translated by accessing the page table, yielding a 34 bit physical…
Joshua McKelvey
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0 answers

How do I reverse a 32 bit register in riscV (32 bit), is there a command for it?

I am using the venus simulator for writing code. I can't find a specific instruction for rotation or reversing a register.
fortune7
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RISC-V: operation with a0 changes other register values

I'm currently doing a small project on risc-v. The problem is that, in a function, when I do something like this, foo: ... lw a3, 4(sp) srli a2, a2, 16 srli a4, a4, 16 add a0, a2, a4 ret after executing add a0, a2, a4…
TAYTAY1313
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Unrecognized opcode in creating custom RISC-V instruction

I've downloaded the rocket-chip repo and the corresponding rocket-tools repo. Everything works just fine when I initially build everything. I've created my own tightly coupled accelerator for the AES algorithm and want to test it using the custom-0…
ttle
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RISC-V (RV32I) - SCALL/ECALL, SBREAK/EBREAK, FENCE, FENCE.I

I am trying to understand how does and what does the following instructions do for RISC-V (RV32I with only machine privilege specifically): SCALL/ECALL SBREAK/EBREAK, FENCE FENCE.I
Zackary Lyman
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Compiling rv32i Code includes compressed Instructions

Im trying to compile bland c code to an elf format executable by a RV32i processor. However when I enable optimizations (-Os or -O2) the resulting assembly contains compressed Instructions which I can not execute. All my selfmade code is being…
Sun.
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1 answer

RISC-V Assembly language. Only printing zero

The following code is supposed to take two lists and put them into one big list (C[10]) and being a beginner in assembly I am unsure as to how to check if my output is correct. I tried implementing a print to check if the left half works but it only…
ZeinZebib
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