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Looking at the AVR instruction set there are four instructions added in 2010

LAC load and clear
LAS load and set
LAT load and toggle
XCH load and exchange

  1. Does anyone know what chips have these instructions

  2. What tools support these instructions

  3. More information on what they do

    (Z) <- Rd v (Z), Rd <- (Z)

does that imply that Rd and (Z) get the same value or does Rd get the pre-modified value of what was pointed to by Z?

unwind
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old_timer
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  • It does eXCHange Rd and the value pointed to by Z, obviously. – Stefan Paul Noack Jan 19 '12 at 10:21
  • Some forums suggest they're probably avaliable on the [XMEGA series of AVR microcontrollers](http://www.atmel.com/dyn/products/devices.asp?category_id=163&family_id=607&subfamily_id=1965) only. – Stefan Paul Noack Jan 19 '12 at 10:29
  • not obvious yet, the xmega docs do not show the instruction in the list. the most recent had its last update before the instruction set manual had these added. – old_timer Jan 19 '12 at 14:29
  • XCH is obvious the other three LAx are not necessarily. Unlike other instructions these dont have much information, appear to have been inserted in a quick, "dont forget to document these" kind of way rather than taking the time to make them complete and consistent with the rest of the manual. – old_timer Jan 19 '12 at 14:31
  • Hm.. someone should test them on the real hardware so we know what they do. – Stefan Paul Noack Jan 19 '12 at 16:02
  • I have this xmega http://www.sparkfun.com/products/9546 and it took a bit to rig up a pdi programmer but I have that going and it appears as if this xmega does not support these instructions. I tried las, lac and xch and neither the Z register, the location pointed to by Z nor the rd register in the instruction are modified. It doesnt hang or otherwise get upset about an undefined instruction it seems to just be flywheeling though it like a nop. – old_timer Jan 24 '12 at 18:43

2 Answers2

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These are probably not around in current (as of initial question) chips, but all have a common theme - atomic memory operations. Their purpose is typically for synchronisation between threads, and their inclusion at an instruction set level probably indicates that Atmel are planning to launch a multi-core AVR chip. Since they're specified now tool vendors can add them to assemblers already, but they won't make a big deal of that until chips have the instructions. (Edit: As it turns out, the other core is the USB peripheral, not a CPU. Thanks to avakar for that information.)

The behaviour, as I read it from the Atmel AVR 8-bit Instruction Set Manual:

LAC - Load and Clear, loads memory contents *Z into register Rd while simultaneously clearing bits in *Z that were set in Rd.

LAS - Load And Set simultaneously sets bits in a memory location that were set in a register, and loads the register with the prior contents of the memory location. Very useful for single-bit mutexes, for instance.

LAT - Load And Toggle; like LAS, but instead of bitwise or, it uses bitwise xor, thus toggling bits.

XCH - Exchange; simply exchanges memory and register contents.

All of them are RAM access instructions (07/2014 reference states they take two cycles), which combine operations so they could also make code that needs RAM faster than it currently is.

Yann Vernier
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  • these avr docs I have been combing through lately, both for my instruction set simulator and for programming the xmega via pdi, are loaded with typos and other mistakes. I assume the lac is missing ",Rd – old_timer Jan 25 '12 at 15:49
  • multi-core AVR? That would be super-awesome. – Stefan Paul Noack Jan 26 '12 at 08:22
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    I'm afraid the instructions were not added for another CPU core, but rather for the USB peripheral, which uses SRAM to store endpoint control/status registers. The instructions are missing in the early A and D models, but are present in AU and newer ones. – avakar Feb 06 '13 at 18:08
  • Even ignoring true multi-thread, these instructions are also useful to avoid races with interrupt handlers. Often you end up doing something like CLI; MOV; CBI/SBI; STI when now you could avoid that and use a single LAC or LAS instruction. – LeoNerd May 09 '15 at 22:38
  • Do you have a link to the instruction reference that documents these instructions? – Conrad Meyer Aug 30 '15 at 19:42
  • Link added in answer. – Yann Vernier Aug 31 '15 at 07:21
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Small but important detail to emphasize: the LAS, LAC and LAT instructions work when Z points to "real" SRAM only. That is not (memory mapped) registers etc. So, in fact, these are useful either for your own (OS) data or XMega USB module, no other peripherals and modules.

It is a pity (as it would be really handy for manipulating PMIC.CTRL flags for example), but it really does not work. Tested. It looks like that LAS, LAC and LAT has the same effect as XCH (exchange between Rd and (Z) but no bit twiddling) when applied on memory mapped registers.

Martin
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