x86 help for rotating significant bits

Question

with x being some integer stored in ebx... How does one rotate the 4 most significant bits by 1, while preserving the 4 least significant bits? where 0xABCDEF12 is rotated to 0xDABCEF12

Answer 1

You're talking about nibbles (hex digits), not bits. 4 nibbles is 16 bits, and x86 does have 16-bit operand-size available for rotate, so you just need to put the bits you want to rotate in the low 16 of a register.

bswap  ebx      # ABCDEF12 -> 12 EF CD AB
ror    bx, 4    # CDAB -> BCDA   (high half unmodified)
bswap  ebx      # 12 EF BC DA -> DABCEF12   (partial-register stall on Core2 / Nehalem)

This is efficient on all x86 CPUs other than Intel P6-family, where the partial-register stall sucks (from reading EBX after writing BX).

Also note that bswap r32 on Core2 and earlier Intel P6 CPUs is 2 uops, thus slower than ror r32, imm8. But you'd avoid this because of the partial-register stall on P6-family anyway. On Skylake, for example, bswap is nice for throughput because it runs on p1 / p5, while rotate runs on p0 / p6, so if you're bottlenecked on throughput of this sequence, rather than latency, it can overlap with itself. If you're overlapping mostly with other surrounding code (not this in a right loop), then you can choose between ror ebx,16 or bswap ebx to balance execution-port pressure if necessary.

Of course, if you were doing just this in a tight loop over an array, don't load the whole element in the first place, just ror word [mem+2], 4 to rotate the high word of a dword in memory. (But don't do this right before loading that array element, because it would cause a store-forwarding stall from the 16-bit store at the end of the read-modify-write forwarding to a wider 32-bit load. Memory-destination rotate is only a good idea if the value is staying in memory and that's all you're doing with it for now.)

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Alternatively, you could shift, mask, and OR to put bits where they belong. I think this would take more instructions and longer than a 3-cycle latency chain. (Or 4-cycle on Sandybridge pre-Ivybridge, where AX is still renamed separately from RAX, but a merging uop can be inserted without stalling.) But do this anyway if you need it to be efficient on Nehalem.

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AVX512F has variable-count rotate (VPRORVD, but not for 16-bit element size (not even with AVX512BW or AVX512VBMI), otherwise you could use a count vector that rotated the top word of each dword by 4, but the bottom word by 0.

AVX512VBMI2 (expected in Ice Lake) has a SIMD version of SHLD, which you can use as a rotate: VPSHRDVW works on word elements:

section .rodata
    rotate_constant:  dw 0, 4

section .text
vpbroadcastd   xmm1, [rotate_constant]   ; 32-bit broadcast of [4, 0]

# rotate the high 16-bit of every dword element in xmm0 (or ymm0 or zmm0)
vpshrdvw       xmm0,xmm0, xmm1

vpshrdvw can't use a broadcast memory operand anyway (unlike the dword and qword versions), and if it could it would be a 16-bit broadcast, not 32-bit.