My exercise: •Calculate the maximum delay possible using three loops @ 1 MHz clock frequency. (Answer 49.94 s)
delay: ldi r23,$FF ;Initialise 3rd loop counter
loop3: ldi r24,$FF ;Initialise 2nd loop counter
loop2: ldi r25,$FF ;Initialise 1st loop counter
loop1: dec r25 ;Decrement the 1st loop counter
brne loop1 ;and continue to decrement until 1st loop counter = 0
dec r24 ;Decrement the 2nd loop counter
brne loop2 ;If the 2nd loop counter is not equal to zero repeat the 1st loop, else continue
dec r23
brne loop3
ret ;Return
I'm trying to calculate the maximum delay using those 3 loops the answer apparently is 49.94 s and I'm really struggling it was much simpler with 2 nested loops.
Here is what I've tried, but the answer is way off.
33*((255*3)-1) + 17*((33*3)-1) + 11*3
ldi
- 1 clock cycle, brne
1 or 2 clock cycles
Architecture: ATmega8535