Concise SSE and MMX instruction reference with latencies and throughput

Question

I am trying to optimize some arithmetic by using the MMX and SSE instruction sets with inline assembly. However, I have been unable to find good references for the timings and usages of these enhanced instruction sets. Could you please help me find references that contain information about the throughput, latency, operands, and perhaps short descriptions of the instructions?

So far, I have found:

Intel Instruction References Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2A and Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2B

Intel Optimization Guide http://www.intel.com/Assets/PDF/manual/248966.pdf

Timings of Integer Operations http://gmplib.org/~tege/x86-timing.pdf

score 10 · Accepted Answer · answered Jun 02 '10 at 22:12

The Intel Instruction Reference should provide an adequate guide to what these instructions actually do, I would have thought? It has pseudocode for each one, a description of its operation, and in some cases even a little diagram of a representative case.

For timings, there's no official guide that I'm aware of. Agner Fog's page is the standard reference:

http://www.agner.org/optimize/

The Agner guide is great. Exactly what I need. – Joe Jun 02 '10 at 23:14 — Joe, Jun 02 '10 at 23:14

score 7 · Answer 2 · answered Jul 13 '11 at 07:15

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The Intel's Intrinsic Guide (at the bottom left of the AVX page), is a well-organized searchable tool, where you can narrow down by SSE version and/or instruction type, e.g., FP arithmetic or Integer Logical.

For each instruction, it also shows a latency/throughput table by CPU and by parameters.

answered Jul 13 '11 at 07:15

hrr

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It's the best I've found for seeing what instructions might do what you want. Other guides are great for detailing exactly what each ASM instruction does, but that takes so much space that you can't get an overview. I was hoping there'd be something similar to the intrinsics guide, but for asm directly. Still, it's mostly a 1:1 mapping. – Peter Cordes Jan 20 '15 at 19:27

score 1 · Answer 3 · answered Jul 13 '11 at 08:30

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The timing are in the "Intel Optimization Guide"; see Appendix C for throughput and latencies for each instruction per CPU architecture.

answered Jul 13 '11 at 08:30

Jasper Bekkers

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Concise SSE and MMX instruction reference with latencies and throughput

3 Answers3