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How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again.

For example 0.3545 = 2^-2 + 2^-4 + ...

I have question about another way, like this. I don't know where does the minus (-) comes from:

0.46194 = 2^-1 - 2^-5 - 2^-7 + 2^-10.

I have just look this from someone. but as you way, that is represented like this

0.46194 = 2^-2 + 2^-3 + 2^-4 + 2^-6 + 2^-7 + 2^-10 + .... .

I don't understand how does it know the minus is used it?

How do we know when the minus needed to it? Also how can I apply to verilog RTL?

UPDATE : I understand the concept the using minus in operation. But Is there any other way to equation or methodologies what to make reduce expression what multiplying with power of 2?

UPDATE : how can we use this method in verilog? for example, I have leaned 0.46194 = 2^-1 - 2^-5 - 2^-7 + 2^-10. then this code was written like this in verilog. 0.011101101 ='hED = 'd237. So the point of the question is how can we apply it to application in verilog?

UPDATE : Sir Would you please check this one? there are a little difference result.

0.46194 = 0.011101101. I just tried like this

0.011101101

0.100T10T01

= 2^-1 - 2^-4 + 2^-5 - 2^-7 + 2^-9. = 0.462890625

Something different. What do I wrong?

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BONGKA
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    @BONGKA The reason for using minus is to have fewer terms, hence fewer addition operations. This makes sense when performing multiplication without a multiplier circuit. – Potatoswatter Feb 07 '15 at 04:00
  • @Potatoswatter Yes it is what exactly I want the part of answer. Thanks. My question is how know ? is there any equation ? I want to know the way what fewer addition operations. Is there any method to reduce operations? – BONGKA Feb 07 '15 at 04:29
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    I've taken the liberty of removing extraneous content from the question. I'll write up the process now. – Potatoswatter Feb 07 '15 at 04:41
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    My previously link should have answered questions on how to do this on verilog. If not, can you clarify or ask another question. NB: do not forget to upvote all helpful questions and answers. thanks. – Morgan Feb 07 '15 at 10:07
  • @Morgan Sir, Did you mean this link? http://stackoverflow.com/questions/28163103/how-much-have-xxx-precision-binary-fixed-point-representation – BONGKA Feb 07 '15 at 13:39
  • I got it, I want to upvote to all. but my reputation under 15. so I can't do that except for receiving the Thanks message. – BONGKA Feb 07 '15 at 14:00
  • Sir the point of my question is different. the point is that how can I apply fixed fraction to the integer. – BONGKA Feb 07 '15 at 14:18
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    It is good practise to clean up comments after they have served there purpose, to leave the site as a clean Question and Answer. Rolling relevant information in to the question/answer. I will occasionally visit old questions and flag comments as obsolete so they can be cleaned up. This is not a reflection that the comment was bad, and it does not hurt your reputation. Comments by there nature are intend to be temporary, if you notice some of your comments disappearing it is not personnel just tidying up. – Morgan Feb 07 '15 at 14:46
  • @Morgan Sir Thanks. I think you are great person. anyway. I have been leaving the new question.http://stackoverflow.com/questions/28383416/how-can-i-apply-fixed-fraction-to-the-integer – BONGKA Feb 07 '15 at 14:52
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    oh shucks you're making me blush. Glad to help, I remember how I struggled when getting started, so just trying to pay it back. Hope the other answer helps. – Morgan Feb 07 '15 at 15:21
  • added to answer to cover your update – Morgan Feb 07 '15 at 17:38

2 Answers2

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Multiplication of a variable by a constant is often implemented by adding the variable to shifted versions of itself. This is much cheaper to put on an FPGA than a multiplier circuit accepting two variables.

You can get further savings when there's a sequence of 1-bits in the constant, by using subtraction as well. (A subtraction circuit is only equally expensive as addition.)

Consider the number 30 = 11110. It's equal to 16 + 8 + 4 + 2, but it's also equal to 32 - 2.

In general, a sequence of multiplicand 1-bits, or the sum of several successive powers of two, can be formed by adding the first power of two after the most significant bit, and subtracting the least significant bit. Hence, instead of 16x + ... + 2x, use 32x - 2x.

It doesn't matter if the sequence of 1-bits is part of a fraction or an integer. You're just applying the identity 2^a = 1 + ∑2^0 ... 2^(a-1), in other worsd ∑2^0 ... 2^a = 2^(a+1) - 1.

Potatoswatter
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  • Thanks, I have some off-topic 2 query by using your answer. 1. what if I want to porting to verilog 0.46194. how does it usually expressed to verilog? 2. What if I want to calculate with 0.46194 by X(integer). What usually expression is used into RTL (verilog)? – BONGKA Feb 07 '15 at 05:05
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    @BONGKA You might ask that as a separate question. I'm not much of a Verilog hacker. Back in school days, when I actually did this kind of thing, I mostly just designed the circuit on paper and then entered the RTL in the simplest way possible. – Potatoswatter Feb 07 '15 at 05:16
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    @BONGKA In the meantime, if this answered this question, please click the up arrow and the checkmark so I get points :) . – Potatoswatter Feb 07 '15 at 05:18
  • I get it. don't worry about it. Thanks. – BONGKA Feb 07 '15 at 05:20
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In a 4 bit base 2 number can have these values:

Base 2: Unsigned 4 bit integer, 
2^3  2^2  2^1  2^0  
  8    4    2    1

If we have a 0111 it represents 7. If we were to multiply by this number using a shift add architecture it would take 3 clockcycles (3 shift and adds).

An optimisation to this is called CSD (Canonical Signed Digit. It allows minus one to be present in the 'binary numbers'. We shall represent -1 as one bar, or T as that looks like a one with a bar over the top.

100T represents 8 - 1 which is the same as 0111. It can be observed that long runs of 1's can be replaced with a the 0 that ends the run becoming 1 and the first 1 of the run becoming a -1, (T).

An example of conversion:

00111101111
01000T1000T

But if passed in two section we would get :

00111101111
0011111000T
010000T000T

We have taken a number that would take 8 clock cycles or 8 blocks of logic to compute and turned it into 3.

Related questions to fixed point values in Verilog x precision binary fixed point representation? and verilog-floating-points-multiplication.

To cover the follow up question:

To answer the follow up section about your question on CSD conversion. I will look at them as pure integers to simplify the numbers, this is the same as multiplying the values by 2^9 (9 fractional bits).

256  128 64 32 16 8 4 2 1
  0    1  1  1  0 1 1 0 1

128 + 64 +32 + 8 +4 +1 => 237

Now with your CSD conversion:

256  128 64 32 16 8 4 2 1
  1    0  0  T  1 0 T 0 1

256  -32 + 16 - 4 + 1 => 237

You can see your conversion was correct. I get 237* 2^-9 as 0.462890625, which matches your answer when converted back to fractional. The 0.46194 that you started with must have been a rounded version, or when quantised to 9 fractional bits gets truncated. This error is known as quantisation error. The most important thing here though is that you got the CSD conversion correct.

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Morgan
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  • Sir, I fully understand what you said, I really appreciate your activities. But I have some query about How can I represent to verilog? How can use it in verilog? – BONGKA Feb 07 '15 at 11:17
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    @BONGKA, I would not bother. It is very good for constants but the synthesis tools will do this automatically for you, and it just makes the code harder to understand. other wise you have to encode each shift as an add or subtract. – Morgan Feb 07 '15 at 13:21
  • Sir, But I think the important things are chip size and speed and area than reuse. But these way also be capsulized as being IP. I mean If I make concrete code(don't need to fix or there is no bugs). it is valuable as itself. But I can't ignore your comments. I agree what you said. – BONGKA Feb 07 '15 at 13:32